Memory Systems Overview
Q-Memory System Architecture
Section titled “Q-Memory System Architecture”Q-Memory has evolved from a resistive non-volatile memory system into a silicon photonic quantum computing platform. This page describes how the new system is organised, how information is stored and processed optically, and how the photonic and electronic layers are integrated.
What Changed
Section titled “What Changed”The previous Q-Memory architecture stored information as resistance states in a material layer — a non-volatile approach with fast writes and zero standby power. Those principles carried forward into the new platform. But the underlying substrate has changed fundamentally.
In the photonic platform, information is carried and processed by single photons — individual particles of light — routed through a programmable network of optical waveguides on a chip. The storage and memory functions now operate at the level of optical phase: the positions of programmable optical elements define the computation, and advanced optical memory materials hold those positions without ongoing power.
System Structure
Section titled “System Structure”The platform is organised into five functional subsystems:
1. Optical Waveguide Network
Section titled “1. Optical Waveguide Network”The primary information-carrying medium. Single photons travel through ultra-low-loss optical waveguides etched into the chip. A programmable mesh of beam splitters and phase-shifting elements routes photons and applies interference operations — equivalent to quantum logic gates or neural network matrix operations.
The waveguide material is chosen for extremely low optical propagation loss — measured in fractions of a decibel per metre — which is essential for maintaining photon fidelity over the chip.
2. Non-Volatile Optical Memory
Section titled “2. Non-Volatile Optical Memory”Programmable elements in the optical network must be held at precise phase values to execute a computation. In conventional photonic systems, this requires continuous electrical power to maintain each element’s position.
The new platform uses optical memory materials — materials that can be switched between stable states using brief optical or electrical pulses, then remain in that state indefinitely without any power. This eliminates the continuous power consumption of the control layer, which in a large chip can otherwise run into hundreds of watts.
Each element can hold multiple distinguishable states — providing fine-grained phase control without ongoing energy use.
3. Photon Source
Section titled “3. Photon Source”Quantum computation and quantum communications require individual photons and entangled photon pairs. The chip integrates on-chip photon sources that generate these at telecom wavelengths:
- Phase 0: External photon sources coupled to the chip via optical fibres
- Phase 1+: On-chip photon pair sources integrated into the waveguide layer, eliminating the need for external laser coupling for quantum operations
4. Detection Subsystem
Section titled “4. Detection Subsystem”Single-photon detectors at the output of each waveguide path capture photons and convert their arrival into classical electrical signals. High detection efficiency is critical — lost photons represent lost quantum information.
The highest-performance detectors require mild cryogenic cooling (achievable with a compact closed-cycle cooler), while room-temperature detectors are available for characterisation and non-quantum-critical paths.
5. CMOS Electronic Control Layer
Section titled “5. CMOS Electronic Control Layer”Classical electronics sit alongside the photonic layer, performing:
- Drive: Generating the electrical signals that control each programmable optical element
- Readout: Amplifying and digitising the output of each photon detector
- Feed-forward: Reading detector results and applying corrections to elements further along the chip — within nanoseconds — enabling adaptive quantum logic even when individual operations succeed probabilistically
- Calibration: Compensating for thermal drift and fabrication variation to keep the optical network precisely programmed
The electronics are co-integrated with the photonic layer using a standard CMOS foundry process, enabling compact packaging and fast signal paths between the two layers.
Competitive Positioning
Section titled “Competitive Positioning”| Aspect | Conventional Quantum Computing | Q-Memory Photonic Platform |
|---|---|---|
| Operating temperature | ~10 mK (dilution refrigerator) | Room temperature (photonic core) |
| Cooling infrastructure | Building-scale (~$1M+) | Compact cryo-insert (detector only) |
| AI acceleration | Separate GPU hardware | Same optical hardware |
| Non-volatile memory | External DRAM/SSD | Integrated optical memory layer |
| Fabrication process | Specialised superconducting process | CMOS-compatible photonic foundry |
Key Advantages for Target Applications
Section titled “Key Advantages for Target Applications”Quantum Computing
Section titled “Quantum Computing”- Room-temperature operation for the core computing layer
- Scalable to large numbers of optical modes using standard chip manufacturing
- Entangled photon pair generation integrated on-chip
- Real-time feed-forward corrections enable fault-tolerant operation
AI Acceleration
Section titled “AI Acceleration”- The same programmable optical network that runs quantum algorithms performs neural network matrix operations
- Power consumption for large-scale optical matrix computation is significantly lower than equivalent GPU workloads
- Non-volatile optical memory eliminates the power overhead of continuously driving programmable elements
Quantum Communications
Section titled “Quantum Communications”- On-chip entangled photon pair generation is directly usable for quantum key distribution
- Telecom wavelength operation is compatible with existing fibre infrastructure
- Compact, CMOS-fabricated platform enables deployment beyond laboratory settings
Capacity and Scale
Section titled “Capacity and Scale”| Phase | Optical Mode Count | Key Capability |
|---|---|---|
| Phase 0 | Small proof-of-concept mesh | Component validation; optical loss characterisation |
| Phase 1 | ~64 modes | On-chip quantum operations; photonic AI demo |
| Phase 2 | ~256 modes (multi-chiplet) | Fault-tolerant quantum circuits; AI training acceleration |
Non-Volatile Optical Memory Detail
Section titled “Non-Volatile Optical Memory Detail”The optical memory layer is a key differentiator of the platform. Compared to continuously driven phase control:
| Property | Conventional Phase Control | Non-Volatile Optical Memory |
|---|---|---|
| Static power per element | ~15 mW | 0 W |
| Power for 256 elements | ~3.8 W | 0 W |
| State retention | Volatile (power required) | Non-volatile (indefinite) |
| Reprogrammability | Continuous | Pulse-based switching |
| Number of states | Continuous analog | Multiple discrete levels |
For large programmable optical networks running AI inference workloads — where the same weights are used for many sequential computations — non-volatile optical memory eliminates the dominant source of static power consumption.