Memory Array Architecture

Memory Array Architecture

Crossbar Array Topology

The DP-MLM memory uses a crossbar architecture for efficient area utilization and simplified addressing.

Array Specifications

• Subarray size: 512 × 512 cells (256K cells per subarray)
• Cell pitch: 500nm (F = 50nm → 10F²)
• Subarray area: 0.065 mm²
• Total chip: 64 subarrays = 16M cells = 208 Mbit

Device Selection Scheme

Challenge

Crossbar arrays suffer from “sneak path” current through unselected cells.

Selector Options

1. Ovonic Threshold Switch (OTS) - Preferred

• Material: Ge-Se-As-Te
• Thickness: 20nm
• Threshold voltage: 1V
• On-resistance: < 1kΩ

2. PN Diode

• More area, but proven technology
• Forward bias: 0.7V
• Reverse blocking: > 5V

Addressing Scheme

Hierarchical Decoder

13-bit Address Input
├─── [8:0] → Row Decoder (512 wordlines)
└─── [12:9] → Column Decoder (512 bitlines)

Advantages:

• Low transistor count: 536 vs 4608 for full decoder
• Faster: 3 levels vs 9 levels
• Lower power consumption

Array Size Scaling

Array Size	Die Area	Devices	Control Lines	Total Pins
16×16	8μm × 8μm	256	16+16	32
128×128	64μm × 64μm	16,384	128+128	256
1K×1K	0.5mm × 0.5mm	1M	1024+1024	2048

Parasitic Management

Parasitic Budget per Device:

• Interconnect resistance: 1kΩ
• Interconnect capacitance: 50fF
• Coupling capacitance: 5fF
• Via resistance: 50Ω (2 vias per device)

Sneak Path Mitigation:

• Selector device ensures < 1nA sneak current
• Minimizes cross-talk between cells
• Enables reliable multi-level operation