Photonic Network Architecture

Photonic Network Architecture

The core of the Q-Memory platform is a programmable optical network — a chip-scale mesh of beam splitters and phase-shifting elements that routes and interferes single photons to perform computation. This page describes the architecture of that network, how it is physically constructed, and how it scales.

The Programmable Optical Mesh

The central computing element is a grid of Mach-Zehnder interferometer (MZI) units — each a pair of beam splitters connected by two waveguide arms with programmable phase elements. By setting the phase difference between the two arms, each unit can split photons in any ratio from fully transmitted to fully reflected, and apply any phase relationship between outputs.

A network of these units — arranged in a specific pattern called a Clements or Reck architecture — can implement any linear optical transformation on N modes. This universality is what makes the mesh useful for both quantum computing (implementing quantum gates) and AI (implementing matrix multiplications).

Mesh Properties

• Universal: Any N-mode linear optical operation can be programmed
• Reconfigurable: Reprogramming the phase elements changes the computation
• Non-volatile programmability: Optical memory materials lock element positions without continuous power
• Low loss per element: Each beam splitter contributes only a small fraction of optical loss, enabling large meshes

Phase 0 Configuration

The Phase 0 proof-of-concept die uses a 4-mode mesh — the smallest configuration that validates every critical component and demonstrates programmable multi-mode optical operations:

• 6 MZI units (the minimum for a complete 4-mode universal mesh)
• 4 optical input ports and 4 optical output ports
• Each MZI has two programmable phase elements driven by on-chip microheaters

This small scale is intentional: it allows each component to be individually tested without the complexity of a large integrated system.

Phase 1+ Configuration

As the platform matures, the mesh grows:

Phase	Mode Count	MZI Count	Key Feature
Phase 0	4	6	Proof-of-concept; component validation
Phase 1	~64	~2016	On-chip photon sources; CMOS co-integrated control
Phase 2	~256	~32,640	Multi-chiplet; fault-tolerant quantum operations

Physical Layer Stack

The chip is built as a vertical stack of functional layers:

Layer 1: Substrate

The mechanical base that all other layers are built on — a standard semiconductor wafer.

Layer 2: Isolation Layer

A thick oxide layer that prevents optical energy from leaking downward into the substrate — critical for maintaining low waveguide loss.

Layer 3: Optical Waveguide Core

The primary photon-carrying layer. Waveguides are etched from silicon nitride — a material chosen for its extremely low optical propagation loss (orders of magnitude lower than conventional silicon waveguides), transparency across a wide wavelength range, and compatibility with standard foundry processes.

Waveguide geometry is designed for single-mode operation at telecom wavelengths, minimising coupling between adjacent paths.

Layer 4: Programmable Phase Layer

Phase-shifting elements are placed above or adjacent to the waveguide core. Multiple phase-shifting technologies are available:

• Thermal phase shifters: Current through a resistive heater element changes the local refractive index; well-characterised, moderate speed, continuous power required
• Electro-optic phase shifters: Voltage-induced refractive index change; ultra-fast (nanosecond-scale), essential for feed-forward operations
• Non-volatile optical memory elements: Material phase-change switches element state permanently with zero ongoing power; used where the same configuration runs for extended periods

Layer 5: Photon Source Integration

On-chip photon sources are integrated into ring resonator structures in the waveguide layer. Photon pair generation occurs through nonlinear optical processes driven by pump light coupled into the ring.

For Phase 0, photon sources are external — coupled via fibre arrays at the chip edge.

Layer 6: Detection Layer

Photon detectors are integrated at output waveguide terminations. High-efficiency single-photon detection requires detectors operating at low temperature; room-temperature detectors are available for lower-sensitivity applications.

Layer 7: CMOS Electronics

Classical control electronics are either co-fabricated on the same wafer (in more advanced process nodes) or bonded above the photonic layer as a separate chiplet. This layer contains the digital-to-analogue converters that drive phase elements, the analogue-to-digital converters that sample detector outputs, and the real-time logic that applies feed-forward corrections.

Layer 8: Metal Interconnect

Standard back-end-of-line metal routing connects the photonic layer components to the CMOS electronics and to the chip’s external pads.

Optical Input/Output

Photons enter and exit the chip through edge couplers — tapered waveguide structures at the chip facet that efficiently transfer light between on-chip waveguides and optical fibres.

For Phase 0, fibres are arranged in a standard V-groove array attached to the chip edge, with input and output ports on opposite faces. The coupling loss per facet is targeted at approximately 1 dB — a carefully engineered transition between the very tight on-chip waveguide mode and the larger fibre mode.

Loss Budget

Fault-tolerant quantum computing places strict requirements on how much photon loss is acceptable across the entire system. Each lost photon represents a failure in that computational path. The total loss across every component — waveguide routing, beam splitters, detectors, couplers — must remain below a tight threshold per photon for reliable operation.

This loss budget drives the material choice for waveguides (silicon nitride over silicon), the edge coupler design, the detector efficiency target, and the maximum chip size at each phase.

Yield and Scalability

Photonic chips have specific yield characteristics different from electronic chips:

• Particle contamination causes point defects that scatter photons at specific locations
• Lithographic variation changes beam splitter splitting ratios uniformly across a die
• Dicing damage threatens edge couplers at chip boundaries

For small Phase 0 dies, the dominant yield factor is lithographic variation — which affects beam splitter accuracy across the mesh. This is characterised in Phase 0 through dedicated test structures that measure splitting ratios across multiple variants.

For Phase 2 multi-chiplet systems, individual chiplets are tested before assembly, and only known-good dies are integrated — similar to chiplet-based approaches in advanced electronic packaging.